Generally stated, a clock generator should generate an output clock signal with an exactly defined frequency and a low frequency and phase jitter. Low frequency and phase jitter means that the frequency and the phase of the output clock signal have low deviations in the frequency and in the phase compared with an ideal expected clock signal.
The output signal of a clock generator is generated by a phase-locked loop (PLL). The PLL has two main functions. The first one is to generate the output signal by performing a frequency multiplication of the input clock signal. The second one is to generate a clock signal with low frequency and phase jitter.
FIG. 1 shows a block diagram of a conventional phase-locked loop. The phase locked loop of FIG. 1 comprises a phase/frequency detector 105, a charge pump 107, a loop filter 109 and a voltage controlled oscillator 111. The output signal of the voltage controlled oscillator 111 represents an output clock signal 113 of the phase locked loop. The output clock signal 113 is fed to an input of the phase frequency detector 105 via a feedback frequency divider 115. A frequency divider 103 divides an input clock signal 101 and transfers the frequency divided signal to an input of the phase frequency detector 105. The output of the phase frequency detector 105 is transferred via the charge pump 107 and the loop filter 109 to the input of the voltage controlled oscillator 111. The signal input to the voltage controlled oscillator 111 is a voltage representative of the phase difference detected by the phase/frequency detector 105. In general, the voltage is not proportional to the phase difference. The voltage determines the frequency of the voltage controlled oscillator.
For applications with a wide output clock frequency range, the phase locked loop based on the self-biased technique developed by John Maneatis has become a standard solution; see John G. Maneatis: “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE Journal of Solid State Circuits, Vol. 31, No. 11, November 1996, page 1723-1732).
A block diagram of a standard self-biased phase locked loop is shown in FIG. 2. The phase locked loop of FIG. 2 comprises an input frequency divider 203, a feedback frequency divider 215, a phase/frequency detector 205, a first charge pump 217 connected to a first loop filter capacitor 221, a second charge pump 219 connected to a second loop filter capacitor 227, a first bias generator 223, which forms a loop filter resistance, a second bias generator 225 connected to a voltage controlled oscillator 211, which represents a chain of oscillator stages. An input clock signal 201 is transferred to the phase/frequency detector 205 via the input frequency divider 203. An output clock signal 213 from the voltage controlled oscillator 211 is fed back to the phase frequency detector 205 via the feedback frequency divider 215. The signals output from the phase/frequency detector 205 are input to both the first charge pump 217 and the second charge pump 219. The output signal from the first charge pump 217 is input to the first bias generator 223 via the first loop filter capacitor 221. The output signal from the second charge pump 219 is input to the second bias generator 225 via the second loop filter capacitor 227. The first output signal 231 of the first bias generator 223 is input to the second bias generator 225. The second output signal 233 from the first bias generator 223 is input to the first and second charge pump 217 and 219. The second bias generator 225 generates a first and a second output signal 235 and 237, which are both input to the voltage controlled oscillator 211.
Although the self-biased phase locked loop described by John Maneatis has only one bias generator, it has become standard to have a two bias generator topology as shown in FIG. 2. The second bias generator 225 separates the second charge pump 219 connected to the second loop filter capacitor 227 from the voltage controlled oscillator 211. Therefore the influence of current peaks coming from the second charge pump 219 on the jitter of the output clock signal 213 is reduced.
The standard self-biased phase locked loop has two advantages for wide output clock frequency applications. The damping factor is nearly fixed and nearly independent of the process variation. This leads to a very stable circuit. Furthermore, the phase locked loop bandwidth tracks only with the input/output clock frequency and does not have a variation like a non-self-biased phase locked loop. For an input clock signal having a high amount of jitter and distortion it is important to set the PLL loop bandwidth as low as possible in order to filter the higher frequency part of the input clock distortion/jitter out of the output clock signal. If the PLL loop bandwidth tracks only the input/output clock frequency, the filter characteristic is very stable.
FIG. 3 shows a gain curve of the standard self-biased phase locked loop of FIG. 2. The diagram of FIG. 3 depicts the frequency fVCO of the output clock signal 213 from the voltage controlled oscillator 213 versus the control voltage VCTRL at the input of the first charge pump 217. The control voltage VCTRL is defined as the supply voltage Vdd minus the voltage VC1 at the first loop filter capacitor 221;VCTRL=Vdd−VC1.
The current flow into each oscillator stage of the VCO 211 increases as the control voltage VCTRL is increased. Therefore, the oscillation frequency becomes higher. A maximum desired application frequency fmax is reached, if the control voltage is equal to Vmax. A minimum desired application frequency fmin is generated by applying a control voltage Vmin to the input of the VCO 211.
As mentioned above, a major function of the PLL is to generate an output clock signal having a low frequency jitter and a low phase jitter. Phase jitter is the deviation of the output phase from an ideal expected clock phase. Besides other possible causes, two PLL parameters determine the amount of clock jitter. The first one is the current flowing through each oscillator stage and the second one is the VCO gain. The VCO gain is defined as the ratio of the oscillator frequency change Δfvco to the control voltage change ΔVCTRL;VCO−gain=Δfvco/ΔVCTRL.
An increasing oscillator stage current diminishes the noise-power of the transistor noise sources. Therefore, the overall clock jitter is reduced. Consequently, it is always desirable to operate at a high current.
The influence/effect of the noise sources in front of the oscillator on the oscillator output signal is decreased by lowering the VCO gain. Therefore, the overall clock jitter is lowered. Consequently, the VCO gain should be as low as possible.
For a standard self-biased PLL topology, the VCO gain is determined by the maximum desired output frequency and the oscillator stage current is determined by the device current consumption specification.
In wide frequency applications, the output clock jitter performance depends on the output clock frequency. Although the VCO gain is nearly constant for the whole frequency range, the current flowing through the oscillator stages depends on the output clock frequency fvco.
The oscillator stage current is high for high oscillation frequencies. Therefore, the noise-power of the internal transistor noise sources is low. In the end, the overall clock jitter has the lowest value.
If the phase locked loop generates lower oscillation frequencies, the oscillator stage current goes down to a lower value. This lets the noise-power of the internal transistor noise sources become larger and therefore the overall clock jitter increases too.